Solder Interconnect Design Group

5th Semi-Annual Solder Interconnect Design Team Meeting
June 9th - 11th 1997
National Institute of Standards and Technology
Gaithersburg, Maryland

Introduction

Carol Handwerker, Chief, Metallurgy Division, NIST, Gaithersburg, MD

James Warren, Metallurgy Division and Center for Theoretical and Computational Materials Science, NIST, Gaithersburg, MD

Talks Presented

• Utilizing a No Clean Process with Alternative to HASL Coatings in High Volume Production
  Russ Davis and Bjoern Brunner, Ford North Penn Electronics Facility, Landsdale, PA
  
• Electroplated Solder for Flip Chip Bonding of Optoelectronics
  Hongtao Han and Songsheng Tan, AMP Inc., Harrisburg, PA
  
• Adaptive Intelligent Reflow (AIR) using Infra-Red Thermography
  David Whalley, Loughborough University, U.K.
  
• The Wetting Balance Test and Wetting Dynamics
  Tsung-Yu Pan, Ford Research Laboratory, Dearborn, MI
  
• Multiphysics Simulation for Solder Joint Formation
  C. Bailey, D. Wheeler, M. Cross, Center for Numerical Modeling and Process Analysis, 
  University of Greenwich, U.K.
  
• Numerical Simulation and Analysis for Some Solder Interconnect Failure
  Xiaohua Wu, Applied Simulation and Modeling Research,Motorola Inc. Schaumburg, IL
  
• Surface Evolver Calculations of Tombstoning
  Ken Brakke, Department of Mathematics, Susquhana University, Susquhana, PA
  
• Using Surface Evolver to Characterize a Soldering Process
  Daniel J. Lewis, NIST, Gaithersburg, MD
  
• Maximizing Solder Joint Reliability through Optimal Shape Design
  Anand Deshpande, Ganesh Subbarayan, Roop Mahajan, Department of Mechanical Engineering, University of Colorado, Boulder, CO
  
• Meniscus Shape Calculations for Solutions
  F. G. Yost, Sandia National Labs, Albuquerque, NM
  
• Evolver Interface/Solder Design 
  Hamid Eghbalnia, University of Wisconsin, Madison, WI
  
• Neuman Equations for Dissolving Systems
  F. G. Yost, Sandia National Labs, Albuquerque, NM
  
• A Model of Reactive Wetting
  James Warren, W. J. Boettinger, A. R. Roosen, NIST, Gaithersburg, MD

Workshop Highlights

• Evolver integration with existing software packages
• Physica used to make Evolver bookkeeping manageable and to make
  Evolver meta-language easier to write.
• New Java based interface and NIST forms for generation of .fe files.
• Wetting balance and reactive wetting phenomena
• High speed video of wetting balance tests.
• Models for reactive wetting presented by NIST and Sandia.
• Presentation by industrial representatives from Ford, AMP and Motorola
• Presented real solder joint manufacturing problems.
• Use of Evolver in industrial applications
• Surface Evolver used to solve manufacturing problems and characterize 
  manufacturing processes.

Summary

The three-day Solder Interconnect Design Team Workshop (June 9th-11th, 1997) was a great success. The participants listed below include 8 attendees from industry, 8 attendees from academia, and 8 attendees from national laboratories. The Workshop began with thirteen concise talks in which the participants discussed their progress in solder joint modeling and presented industrial problems that warranted the group's attention. Through these talks and less formal group discussions and interactions, the Team members were able to assess the current state of solder interconnect design tools in the electronics industry. This critical assessment was necessary to assess our own progress toward achieving the Team's mission to produce robust, useful software tools for the better design of solder joints.

What follows is an assessment of where we believe the Solder Interconnect Design Team needs to go from here, both in the short and long terms, as well as a schematic of how the various "levels" in the modeling of solder reliability come together.

The Team has identified four levels of modeling solder joints:

which have been addressed by the modeling community with varying degrees of success.

At each of these levels the solder joint designer must grapple with issues of

These two sets form a matrix with unique opportunities and challenges for the circuit board designer. Some tools already exist for board level design, where the concerns of electrical connectivity, functionality, thermal management and materials issues all play a role.

More recently, solder joint design tools have been developed and implemented for solving time critical manufacturing problems (firefighting) for existing packages and board designs, and are now beginning to be used to improve the design and development of new boards and packages.

Using the software package the Surface Evolver (by Ken Brakke) we already have the basic building blocks needed for modeling the geometries of most leaded solder joints that are currently produced by industry. (For more information visit the Team's WWW site at www.ctcms.nist.gov/programs/solder.) In addition we have a model for discrete chip capacitors and resistors from the Tombstoning problem. Although models for leadless ceramic chip carriers and through hole components are not yet available, models similar to these geometries do exist and adding these to the repository should be fairly easy.

A method has been demonstrated to ease the creation of Surface Evolver files, using a widely available finite element pre-processing package to generate the vertices, edges, and facets needed for input. Our next task is to focus on generating the constraints in tandem with the input geometry, so that the creation of Evolver input files will be completely automated. An attempt to implement a JAVA front-end to Evolver has proved difficult, due to the rapid pace of change in the language coupled to the lack of backward incompatibility between different versions of JAVA.

The next modeling step will be to take our Surface Evolver single solder joint models and continue our analysis of the manufacturing process at the component level. Stress and strain analyses of the component leads due to surface tension effects can be calculated with existing software from initial meniscus geometries. This could be realized by systematically changing the component geometries at the board level and attempting to model the resulting solder joints. From this the stability of designs could be ascertained. An excellent example of this was presented by Xiaohua Wu (Motorola).

Moving in another direction, it would be useful to extend University of Greenwich's project on using Surface Evolver calculations for initial solidification geometries. The extension of this idea would be to apply microstructural models to solder joint solidification and reliability in conditions of thermomechanical fatigue. The example of fillet lifting in a plated through-hole geometry was presented by Chris Bailey (U. Greenwich) as a test problem for this modeling technology.

At this meeting we benefited from having representatives from Ford, AMP, Texas Instruments, Heraeus, and Motorola, who provided us with useful information on "real-world" manufacturing and reliability issues. We can always use more manufacturing input. We would like to know what industry needs to successfully produce solder interconnections.

THE TEAM PLANS TO MEET AGAIN THIS WINTER (1998) AT NIST. ALL INTERESTED PARTIES ARE WELCOME TO ATTEND. CONTACT JAMES WARREN FOR MORE INFORMATION.